Week06 - Mojo V3 – Display 7_Segment and UART Tx

Week6
Mojo V3 – Display 7_Segment and UART Tx

          

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6.1)Single 7 Segment Display – Main Schematic

1.ใส่ Decode_7Seg Verilog File 

2.Gen_1Hz Verilog File

3.Main Schematic File

4.Port Input/Output .ucf File

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6.2) 4-Digit 7 Segment Display

1.ใส่  Clock Generate Verilog File

2. Driver 4 Digit Verilog File

3. Main Schematic File

4.Port Input/Output ucf File

ผลที่ได้

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6.3)  MAX7219 Display Control

1.ใส่ test Data 32bit Verilog File

2.Driver MAX7219 VHDL File

3.Main Schematic File

4.Port Input/Output ucf File